Method of making a MOS-gated semiconductor device with a single diffusion
US6080614A · kind A · utility
27Cited by
6References
46Claims
0Family size
Inventors
Key dates
| Filing date | Jun 30, 1997 |
| Grant date | Jun 27, 2000 |
| Priority date | — |
| Expiry date | Jun 30, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/126
Abstract
A method of fabricating a MOS-gated semiconductor device in which arsenic dopant is implanted through a mask to form a first layer, boron dopant is implanted through the mask to form a second layer deeper than the first layer, and in which a single diffusion step diffuses the implanted arsenic and the implanted boron at the same time to form a P+ body region with an N+ source region therein and a P type channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.