Method of manufacturing dynamic random access memory
US6080621A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1998 |
| Grant date | Jun 27, 2000 |
| Priority date | — |
| Expiry date | Oct 1, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/033
Abstract
A method of forming a DRAM capacitor that utilizes cap layers and spacers to surround the gate and bit line so that the necessary contact openings in a DRAM can be formed in two self-aligned contact processing operations. The capacitor of the DRAM is fabricated by forming contact node and openings within an insulating layer above a substrate, and then forming a first conductive layer conformal to the surface profile of the substrate above the substrate structure. Next, spacers are formed on the sidewalls of the conductive layer, and then a second conductive layer is formed filling the spacer between the spacers and over the substrate structure. Thereafter, a portion of the first conductive layer and the second conductive layer is removed to expose the spacers and the insulating layer. Finally, the spacers and the insulating layer are removed to expose a lower electrode structure that comprises the first and the second conductive layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.