Via structure and method of manufacture
US6080660A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 1998 |
| Grant date | Jun 27, 2000 |
| Priority date | — |
| Expiry date | Feb 27, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76805
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a via structure comprising the steps of providing a semiconductor substrate, and then forming conductive line and dielectric layer over the substrate. Next, a photolithographic and a first etching operation are conducted so that an opening in the dielectric layer exposing the conductive line surface is formed. The first etching operation uses several etchants including fluorobutane, which has the highest concentration. Since there is a re-entrance structure at the bottom of the opening, a second etching operation is performed. In the second etching operation, a portion of the conductive line is etched for a fixed time interval to control the degree of etching. Consequently, a slanting surface is formed at the bottom of the opening and the re-entrance structure is eliminated. With a planarized bottom, step coverage of subsequently deposited material is increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.