Method for preventing micromasking in shallow trench isolation process etching
US6080677A · kind A · utility
2Cited by
5References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1997 |
| Grant date | Jun 27, 2000 |
| Priority date | — |
| Expiry date | Dec 30, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An isolation structure on an integrated circuit is formed using a shallow trench isolation process. A layer of buffer oxide is formed on a substrate. A layer of nitride is formed on the layer of buffer oxide. The layer of nitride and the layer of buffer oxide are patterned to form a trench area. The substrate including the trench area is subjected to a plasma comprising H.sub.2 O vapor, and a gaseous fluorocarbon or a fluorinated hydrocarbon gas to clean impurities on the trench area. The substrate is etched to form a trench within the trench area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.