Stacked capacitor memory cell and method of manufacture
US6083788A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 1999 |
| Grant date | Jul 4, 2000 |
| Priority date | — |
| Expiry date | Mar 26, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A DRAM memory cell structure of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) and a stacked capacitor and a method for forming same facilitates low resistance contact between the source/drain of the transistor and a lower electrode of the capacitor. The method in its preferred embodiment uses platinum for the bottom electrode of the capacitor without the need for a diffusion barrier between it and a doped polysilicon plug used to contact the MOSFET. To this end, the formation of the contact is after the deposition of the high dielectric material, such as barium strontium titanate, used to form the dielectric of the capacitor. Also the bottom electrode of the capacitor is partially offset with respect to the polysilicon plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.