Overlay measuring mark and its method
US6083807A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 3, 1999 |
| Grant date | Jul 4, 2000 |
| Priority date | — |
| Expiry date | Aug 3, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This invention discloses an overlay measuring mark and a method of measuring an overlay error of semiconductor used by the overlay measuring mark. This overlay measuring mark comprises a first mark formed on a first layer on a semiconductor substrate and including four bar sets, which form a first square pattern, each of said bar sets at least comprising two parallel bars relatively formed by a first slim pattern; and a second mark formed on a second layer on said first layer and including four bar formed a second square pattern, wherein said four bar relatively are formed by a second slim pattern and said second square is located in and smaller than said first square in a top view.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.