Method for fabricating local interconnect
US6083827A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 1998 |
| Grant date | Jul 4, 2000 |
| Priority date | — |
| Expiry date | Dec 15, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a local interconnect. A gate having a gate oxide layer, a gate polysilicon layer and a cap layer is formed on a provided substrate. A spacer is formed on the sidewall of the gate, and a source/drain region is formed in the substrate. A planarized dielectric layer is formed over the substrate to expose the cap layer. A portion of the dielectric layer and the spacer on one side of the gate is removed to form an opening, so that the source/drain region is exposed. The opening is transformed into a local-interconnect opening by removing the cap layer. A local interconnect is formed by forming a conductive layer in the local-interconnect opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.