HSQ dielectric interlayer
US6083850A · kind A · utility
13Cited by
5References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 18, 1997 |
| Grant date | Jul 4, 2000 |
| Priority date | — |
| Expiry date | Dec 18, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76801
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The use of HSQ as a dielectric interlayer without cracking is achieved by depositing HSQ on a planarized dielectric layer, such as a silicon oxide derived from TEOS or silane. Embodiments include depositing a first HSQ gap fill layer on a patterned metal layer for gap filling leaving a non-planar upper surface. Depositing a thin layer of silicon oxide and planarizing the upper surface as by CMP, and depositing the HSQ dielectric interlayer on the planarized upper surface of the oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.