Jeffrey A. Shields
89Patents
14h-index
110Co-inventors
87Inventor score
Filing activity: Oct 16, 1997 → Apr 6, 2017
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6617215B1 | Memory wordline hard mask | Electricity | 39 | Expired |
| US7776682B1 | Ordered porosity to direct memory element formation | Electricity | 29 | Active |
| US6060384A | Borderless vias with HSQ gap filled patterned metal layers | Electricity | 28 | Expired |
| US6153504A | Method of using a silicon oxynitride ARC for final metal layer | Emerging Cross-Sectional Technologies | 27 | Expired |
| US6522013B1 | Punch-through via with conformal barrier liner | Electricity | 26 | Expired |
| US5866945A | Borderless vias with HSQ gap filled patterned metal layers | Electricity | 26 | Expired |
| US6114766A | Integrated circuit with metal features presenting a larger landing area for vias | Electricity | 21 | Expired |
| US6376877B1 | Double self-aligning shallow trench isolation semiconductor and manufacturing method therefor | Electricity | 19 | Expired |
| US6479348B1 | Method of making memory wordline hard mask extension | Electricity | 17 | Expired |
| US6709924B1 | Fabrication of shallow trench isolation structures with rounded corner and self-aligned gate | Emerging Cross-Sectional Technologies | 16 | Expired |
| US6589709B1 | Process for preventing deformation of patterned photoresist features | Electricity | 15 | Expired |
| US6774432B1 | UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL | Emerging Cross-Sectional Technologies | 15 | Expired |
| US6441418B1 | Spacer narrowed, dual width contact for charge gain reduction | Electricity | 15 | Expired |
| US6087724A | HSQ with high plasma etching resistance surface for borderless vias | Electricity | 14 | Expired |
| US6486506B1 | Flash memory with less susceptibility to charge gain and charge loss | Electricity | 13 | Expired |
| US6653231B2 | Process for reducing the critical dimensions of integrated circuit device features | Electricity | 13 | Expired |
| US6083850A | HSQ dielectric interlayer | Electricity | 13 | Expired |
| US8941089B2 | Resistive switching devices and methods of formation thereof | Electricity | 13 | Active |
| US5958798A | Borderless vias without degradation of HSQ gap fill layers | Electricity | 13 | Expired |
| US6492257B1 | Water vapor plasma for effective low-k dielectric resist stripping | Electricity | 12 | Expired |
| US6083851A | HSQ with high plasma etching resistance surface for borderless vias | Electricity | 12 | Expired |
| US6222761A | Method for minimizing program disturb in a memory cell | Physics | 12 | Expired |
| US7091088B1 | UV-blocking etch stop layer for reducing UV-induced charging of charge storage layer in memory devices in BEOL processing | Emerging Cross-Sectional Technologies | 11 | Expired |
| US6194328A | H2 diffusion barrier formation by nitrogen incorporation in oxide layer | Electricity | 10 | Expired |
| US8866122B1 | Resistive switching devices having a buffer layer and methods of formation thereof | Electricity | 10 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.