Universal alignment marks for semiconductor defect capture and analysis
US6084679A · kind A · utility
62Cited by
1References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 2, 1999 |
| Grant date | Jul 4, 2000 |
| Priority date | — |
| Expiry date | Apr 2, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of using universal alignment marks on a semiconductor wafer that allows the accurate alignment of scanning and analysis tools in relation to the semiconductor wafer. The information in the universal alignment marks are utilized by a vendor generated algorithm incorporated into the respective scanning or analysis tools to accurately position the tool in relation to the semiconductor wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.