Inventor · Fremont, CA, US

Allen S. Yu

55Patents
18h-index
11Co-inventors
73Inventor score

Filing activity: Feb 27, 1998 → Jan 25, 2005

Most-cited inventions

PatentTitleAreaCited byStatus
US6084679A Universal alignment marks for semiconductor defect capture and analysis Electricity 62 Expired
US6605541B1 Pitch reduction using a set of offset masks Electricity 53 Expired
US6025259A Dual damascene process using high selectivity boundary layers Electricity 52 Expired
US6239008A Method of making a density multiplier for semiconductor device manufacturing Electricity 46 Expired
US6448606B1 Semiconductor with increased gate coupling coefficient Electricity 34 Expired
US6291332A Electroless plated semiconductor vias and channels Electricity 32 Expired
US6376312B1 Formation of non-volatile memory device comprised of an array of vertical field effect transistor structures Electricity 32 Expired
US6287968A Method of defining copper seed layer for selective electroless plating processing Electricity 31 Expired
US6377898B1 Automatic defect classification comparator die selection system Electricity 30 Expired
US6274443A Simplified graded LDD transistor using controlled polysilicon gate profile Electricity 27 Expired
US6013570A LDD transistor using novel gate trim technique Electricity 25 Expired
US6091138A Multi-chip packaging using bump technology Electricity 23 Expired
US6864163B1 Fabrication of dual work-function metal gate structure for complementary field effect transistors Electricity 22 Expired
US5985753A Method to manufacture dual damascene using a phantom implant mask Electricity 21 Expired
US6338001B1 In line yield prediction using ADC determined kill ratios die health statistics and die stacking Electricity 21 Expired
US6204133A Self-aligned extension junction for reduced gate channel Electricity 21 Expired
US6103616A Method to manufacture dual damascene structures by utilizing short resist spacers Electricity 20 Expired
US6376877B1 Double self-aligning shallow trench isolation semiconductor and manufacturing method therefor Electricity 19 Expired
US6100593A Multiple chip hybrid package using bump technology Electricity 18 Expired
US6387758B1 Method of making vertical field effect transistor having channel length determined by the thickness of a layer of dummy material Electricity 18 Expired
US6430572B1 Recipe management database system Emerging Cross-Sectional Technologies 17 Expired
US6709924B1 Fabrication of shallow trench isolation structures with rounded corner and self-aligned gate Emerging Cross-Sectional Technologies 16 Expired
US6524916B1 Controlled gate length and gate profile semiconductor device and manufacturing method therefor Electricity 15 Expired
US6191044A Method for forming graded LDD transistor using controlled polysilicon gate profile Electricity 14 Expired
US6177287A Simplified inter database communication system Physics 14 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.