Logic synthesis constraints allocation automating the concurrent engineering flows
US6086621A · kind A · utility
15Cited by
3References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 12, 1998 |
| Grant date | Jul 11, 2000 |
| Priority date | — |
| Expiry date | May 12, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a system allocate a budget to a circuit design. A timing analysis is prepared for a circuit and a budget is automatically allocated to each of the blocks of the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.