Method of manufacturing DRAM capacitor
US6087216A · kind A · utility
6Cited by
4References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 18, 1998 |
| Grant date | Jul 11, 2000 |
| Priority date | — |
| Expiry date | Nov 18, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/315
Abstract
A method of manufacturing a DRAM capacitor utilizes spacers to form a self-aligned node contact, and thus is able to reduce the cross-sectional dimensions of the node contact. Moreover, the spacers are capable of protecting any portion of a bit line that may be exposed due to misalignment when contact opening is formed. Hence, short-circuiting of the device can be prevented. Furthermore, by shaping the lower electrode of the capacitor into a fork-shaped structure with four prongs, the surface area for capacitor coupling is increased, thus increasing the capacitance of the capacitor, as well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.