Bump chip scale semiconductor package
US6091141A · kind A · utility
39Cited by
3References
20Claims
0Family size
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Inventor
Key dates
| Filing date | Dec 29, 1998 |
| Grant date | Jul 18, 2000 |
| Priority date | — |
| Expiry date | Dec 29, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bump chip scale semiconductor package. In the bump chip scale semiconductor package, the chip bumps are directly formed on the chip pads of a semiconductor chip. The above chip bumps are used as the signal input and output terminals of the package and are used as surface mounting joints when the chip is mounted to a mother board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.