Method of minimizing dishing during chemical mechanical polishing of semiconductor metals for making a semiconductor device
US6093656A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 26, 1998 |
| Grant date | Jul 25, 2000 |
| Priority date | — |
| Expiry date | Feb 26, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7684
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for eliminating the dishing effect of the chemical mechanical polishing (CMP) process on wide inlaid conductor leads in the layer of dielectric on a semiconductor device. A silicon dioxide dielectric having narrow and wide trenches is first coated with a blanket deposition of conductor material. The conductor material is coated with a photoresist and patterned with a reverse photo image of the trenches. The photoresist is etched leaving the photoresist over the trenches and the conductor material exposed between the trenches. The conductor material is etched removing the conductor material between the trenches and leaving the original thickness of conductor material over the trenches. The remaining photoresist is removed and the conductor material subject to CMP with the original thickness of conductor material acting to prevent dishing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.