Semiconductor calibration structures and calibration wafers for ascertaining layer alignment during processing and calibrating multiple semiconductor wafer coating systems
US6094965A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 1998 |
| Grant date | Aug 1, 2000 |
| Priority date | — |
| Expiry date | May 29, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/16
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Semiconductor wafer coating system calibration structures and methods are described. In one embodiment, a calibration structure includes a perimetral edge bounding a calibration body. A calibration edge is spaced from the perimetral edge and is positioned over the calibration body. Together, the edges define a distance therebetween which is configured to calibrate a wafer coating system. In a preferred embodiment, the edges define respective termination distances configured to calibrate multiple different wafer coating systems. In another embodiment, a calibration pattern is formed over a semiconductor wafer. A layer of material is formed over the calibration pattern by a coating system, and selected portions thereof removed by the system. The positions of unremoved portions of the layer of material are inspected relative to the calibration pattern to ascertain whether the coating system removed the selected portions within desired tolerances. If not, the coating system is calibrated to within desired tolerances.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.