Scalable MOS field effect transistor
US6096590A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1998 |
| Grant date | Aug 1, 2000 |
| Priority date | — |
| Expiry date | Jun 30, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/86
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A field effect transistor and method for making is described incorporating self aligned source and drain contacts with Schottky metal-to-semiconductor junction and a T-shaped gate or incorporating highly doped semiconductor material for the source and drain contacts different from the channel material to provide etch selectivity and a T-shaped gate or incorporating a metal for the source and drain contacts and the oxide of the metal for the gate dielectric which is self aligned. The invention overcomes the problem of self-aligned high resistance source/drain contacts and a high resistance gate electrode for submicron FET devices which increase as devices are scaled to smaller dimensions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.