Manufacturing process for reducing feature dimensions in a semiconductor
US6096659A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 1998 |
| Grant date | Aug 1, 2000 |
| Priority date | — |
| Expiry date | Apr 13, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/95
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for reducing dimensions of circuit elements in a semiconductor device. The process reduces feature sizes by using an intermediate etchable mask layer between a photo-resistive mask and a layer to be etched. The etchable mask layer below the photo-resistive mask is etched and portions remain which undercut the pattern on the photo-resistive mask. After removing the photo-resistive mask, the remaining mask portions are then used to mask the layer to be etched. By undercutting the photo-resistive mask, the mask portions form a pattern having features with widths that are less than widths of features in the photo-resistive mask. The layer to be etched can then be etched to provide circuit elements with reduced dimensions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.