Method of manufacturing semiconductor structures including a pair of MOSFETs

US6096664A · kind A · utility

Assignees

• Siemens Aktiengesellschaft · DE
• International Business Machines Corporation · US

Inventors

• Thomas Rupp · Stormville, US
• Stephan Kudelka · Radeberg, DE
• Jeffrey P. Gambino · Gresham, US
• Mary E. Weybright · Pleasant Valley, US

Key dates

• Filing date: Aug 6, 1998
• Grant date: Aug 1, 2000
• Expiry date: Aug 6, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0144

Abstract

A method for forming a pair of MOSFETs in different electrically isolated regions of a silicon substrate. Each one of the MOSFETs has a different gate oxide thickness. A first layer of silicon dioxide is grown to a predetermined thickness over the surface of the silicon substrate. One portion of the silicon dioxide layer is over a first isolated region and another portion of the silicon dioxide layer being over a second isolated region. An inorganic layer is formed over the silicon dioxide layer extending over the isolated regions of the silicon substrate. A first portion of the inorganic layer is over the first isolated regions and a second portion of the inorganic layer is over the second isolated regions. A photoresist layer is formed over the inorganic layer. The photoresist layer is patterned with a window over the first portion of the inorganic layer. The photoresist layer covers the second portion of the inorganic layer. The inorganic layer is patterned into an inorganic mask by bringing a etch into contact with the patterned photoresist layer to selectively remove the first portion of the inorganic layer an thereby expose an underlying portion of the surface of the silicon …