Speculative issue of instructions under a load miss shadow
US6098166A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 1998 |
| Grant date | Aug 1, 2000 |
| Priority date | — |
| Expiry date | Apr 10, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for speculatively issuing instructions using an out-of-order processor. A cache miss by a load instruction results in either a reissue of all subsequently issued instructions for an integer instruction stream, or a reissue of only truly dependent instructions for a floating point instruction stream. One version of the technique involves issuing and executing a first instruction, and issuing a second instruction during a speculative time window of the first instruction that occurs after the first instruction is issued. The technique further involves executing the issued second instruction when the first instruction is executed in a first manner, and reissuing the second instruction and executing the reissued second instruction when the first instruction is executed in a second manner that is different than the first manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.