System for designing and manufacturing CMOS inverters by estimating gate RC delay
US6099576A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 2, 1998 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | Mar 2, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for simplifying and expediting estimation of the gate RC delay and/or the determination of transistor widths for a given gate RC delay in a CMOS inverter circuit. The system determines gate RC delay as a function of transistor width. Alternatively, appropriate transistor widths may be determined based on a desired optimum gate RC delay. An analytical expression is established to predict RC induced gate propagation delay as a function of readily available technical parameters in the early stage of design. The analytical expression has been found to describe gate RC delay in CMOS inverter circuits incorporating 0.25 micron (or even smaller) manufacturing technology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.