Method of manufacturing a semiconductor memory device having a trench capacitor
US6100130A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 1997 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | Apr 4, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/038
Abstract
The invention provides a structure which enables a junction leak current to be reduced without reducing a capacitor area. A trench is formed in the surface of a substrate such that it is connected to a conductive region for a transistor. The structure is characterized by comprising a capacitor electrode formed on the inner peripheral surface of the trench and having its upper edge portion located below the conductive region, an insulating layer projecting inward of the trench at least from the upper edge portion of the capacitor electrode to the conductive region, thereby narrowing the diameter of the trench, a capacitor insulating film coated on the capacitor electrode, and a capacitor electrode filling the trench and contacting the capacitor insulating film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.