Method of forming a circuitry isolation region within a semiconductive wafer
US6100162A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 1999 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | May 14, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76205
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a circuitry isolation region within a semiconductive wafer comprises defining active area and isolation area over a semiconductive wafer. Semiconductive wafer material within the isolation area is wet etched using an etch chemistry which forms an isolation trench proximate the active area region having lowestmost corners within the trench which are rounded. Electrically insulating material is formed within the trench over the previously formed round corners. In accordance with another aspect, the semiconductive wafer material within the isolation area is etched using an etch chemistry which is substantially selective relative to semiconductive wafer material within the active area to form an isolation trench proximate the active area region. In accordance with still another aspect, a method of forming a circuitry isolation region within a semiconductive wafer comprises masking an active area region over a semiconductive wafer. The active area region is provided with an impurity doping of a first conductivity type. An impurity of a second conductivity type is provided within the semiconductive wafer proximate the masked active area region. Second conductivity typ…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.