Methods of fabricating silicon carbide power devices by controlled annealing
US6100169A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 1998 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | Jun 8, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/965
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Silicon carbide power devices are fabricated by masking the surface of a silicon carbide substrate to define an opening at the substrate, implanting p-type dopants into the silicon carbide substrate through the opening at implant energy and dosage that form a deep p-type implant, and implanting n-type dopants into the silicon carbide substrate through the opening at implant energy and dosage that form a shallow n-type implant relative to the deep p-type implant. The deep p-type implant and the shallow n-type implant are annealed at less than 1650.degree. C., but preferably more than about 1500.degree.. The annealing preferably takes place for between about five minutes and about thirty minutes. Ramp-up time from room temperature to the anneal temperature is also controlled to be less than about one hundred minutes but more than about thirty minutes. Ramp-down time after annealing is also controlled by decreasing the temperature from the annealing temperature to below about 1500.degree. C. in less than about two minutes. By controlling the ramp-up time, the annealing time and/or temperature and/or the ramp-down time, high performance silicon carbide power devices may be fabricated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.