Forming a self-aligned silicide gate conductor to a greater thickness than junction silicide structures using a dual-salicidation process
US6100173A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 1998 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | Jul 15, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/68
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit fabrication process is provided for using a dual salicidation process to form a silicide gate conductor to a greater thickness than silicide structures formed upon source and drain regions of a transistor. A high K gate dielectric residing between the gate conductor and the substrate substantially inhibits consumption of the junctions during the formation of the silicide gate conductor. In an embodiment, a relatively thick layer of refractory metal is deposited across a transistor arranged upon and within a silicon-based substrate. The transistor includes a polysilicon gate conductor arranged upon a portion of a high K gate dielectric interposed between a pair of source and drain junctions. The refractory metal is heated to convert the polysilicon gate conductor to a silicide gate conductor. After removing the gate dielectric from the source and drain regions, a relatively thin layer of refractory metal is deposited across the topography and heated to form silicide structures upon the source and drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.