Semiconductor device having enhanced gate capacitance by using both high and low dielectric materials
US6100558A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 1998 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | Jul 16, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a MOSFET device is provided. The method includes a step of forming a gate oxide including first and second gate oxide materials. The first gate oxide material has a higher dielectric constant than the second gate oxide material. The first gate oxide material is formed to be over source/drain extension regions of the device; and the second gate oxide material is formed over a channel region of the device. The first gate oxide material has a low dielectric constant and provides for mitigating gate fringing field effects. The second gate oxide material has a high dielectric constant and provides for forming a thick gate oxide over a channel region of the device. Controlled uniform growth of the second gate oxide material is facilitated because of the thickness thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.