Inventor · Campbell, CA, US

Srinath Krishnan

51Patents
17h-index
33Co-inventors
80Inventor score

Filing activity: Dec 19, 1997 → Dec 18, 2015

Most-cited inventions

PatentTitleAreaCited byStatus
US6184112A Method of forming a MOSFET transistor with a shallow abrupt retrograde dopant profile Electricity 127 Expired
US6060364A Fast Mosfet with low-doped source/drain Electricity 124 Expired
US6087208A Method for increasing gate capacitance by using both high and low dielectric gate material Electricity 106 Expired
US6955969B2 Method of growing as a channel region to reduce source/drain junction capacitance Electricity 88 Expired
US5960322A Suppression of boron segregation for shallow source and drain junctions in semiconductors Emerging Cross-Sectional Technologies 53 Expired
US6509613B1 Self-aligned floating body control for SOI device through leakage enhanced buried oxide Electricity 51 Expired
US6548361B1 SOI MOSFET and method of fabrication Electricity 49 Expired
US6611023B1 Field effect transistor with self alligned double gate and method of forming same Electricity 46 Expired
US6466082B1 Circuit technique to deal with floating body effects Electricity 45 Expired
US6204138A Method for fabricating a MOSFET device structure which facilitates mitigation of junction capacitance and floating body effects Electricity 37 Expired
US6512244B1 SOI device with structure for enhancing carrier recombination and method of fabricating same Electricity 35 Expired
US6100558A Semiconductor device having enhanced gate capacitance by using both high and low dielectric materials Electricity 26 Expired
US7071044B1 Method of making a test structure for gate-body current and direct extraction of physical gate length using conventional CMOS Electricity 20 Expired
US6713819B1 SOI MOSFET having amorphized source drain and method of fabrication Electricity 19 Expired
US6589823B1 Silicon-on-insulator (SOI)electrostatic discharge (ESD) protection device with backside contact plug Electricity 18 Expired
US6362063B1 Formation of low thermal budget shallow abrupt junctions for semiconductor devices Electricity 18 Expired
US6238960A Fast MOSFET with low-doped source/drain Electricity 17 Expired
US6399452B1 Method of fabricating transistors with low thermal budget Electricity 15 Expired
US6441433B1 Method of making a multi-thickness silicide SOI device Electricity 15 Expired
US6420767B1 Capacitively coupled DTMOS on SOI Electricity 15 Expired
US6498371B1 Body-tied-to-body SOI CMOS inverter circuit Emerging Cross-Sectional Technologies 14 Expired
US6492209B1 Selectively thin silicon film for creating fully and partially depleted SOI on same wafer Electricity 14 Expired
US6462381B1 Silicon-on-insulator (SOI) electrostatic discharge (ESD) protection device with backside contact opening Electricity 12 Expired
US6429083B1 Removable spacer technology using ion implantation to augment etch rate differences of spacer materials Electricity 11 Expired
US6429054B1 Method of fabricating semiconductor-on-insulator (SOI) device with hyperabrupt source/drain junctions Electricity 11 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.