High speed IC package configuration
US6103547A · kind A · utility
178Cited by
12References
35Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 17, 1997 |
| Grant date | Aug 15, 2000 |
| Priority date | — |
| Expiry date | Jan 17, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Devices and methods for reducing lead inductance in integrated circuit (IC) packages. More specifically to an integrated circuit package configuration for high speed applications where the inductance of the leads is reduced or minimized in high capacity semiconductor device packages. The integrated circuit package assembly comprises a substrate, semiconductor device, insulating covering or coating, if desired, a semiconductor device retainer, lead frame, and wire bond interconnections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.