Method of improving Cu damascene interconnect reliability by laser anneal before barrier polish
US6103624A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 1999 |
| Grant date | Aug 15, 2000 |
| Priority date | — |
| Expiry date | Apr 15, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices with copper interconnects wherein a barrier metal layer is applied over the surface of a dielectric layer with a plurality of trenches. The barrier metal layer lines the trenches. A copper layer is placed over the barrier metal layer and fills the trenches. The part of the copper layer that is not inside the trenches is polished away, making sure that the barrier metal layer is not polished away. The copper layer is laser annealed to increase the grain size, remove seams, and provide a better interface bond between the barrier metal layer and the copper layer. The barrier metal layer protects the dielectric layer during the annealing process. The part of the barrier metal layer that is not in the trenches is removed by polishing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.