Enhanced word line driver to reduce gate capacitance for low voltage applications
US6104665A · kind A · utility
22Cited by
4References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 5, 1999 |
| Grant date | Aug 15, 2000 |
| Priority date | — |
| Expiry date | Apr 5, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An enhanced word line driver circuit suitable for use on integrated circuits such as flash memory devices with voltage boosting includes a load reduction circuit. In response to a boosted voltage, the load reduction circuit decouples a gate capacitance load of deselected enhanced word line drivers from the boost voltage generator. The reduction of capacitive loading decreases power consumption and shortens the voltage boost time of the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.