Method and apparatus for generating memory addresses for testing memory devices
US6104669A · kind A · utility
0Cited by
17References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 22, 1999 |
| Grant date | Aug 15, 2000 |
| Priority date | — |
| Expiry date | Jun 22, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A counter internal to a memory device for generating memory addresses in physical or logical sequence in non-redundant or redundant memory space, counting up or down in increments of the user's choice. The counter may be advantageously used to generate memory addresses for functional testing of the memory cells within the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.