Salphasic timing calibration system for an integrated circuit tester
US6105157A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 30, 1998 |
| Grant date | Aug 15, 2000 |
| Priority date | — |
| Expiry date | Jan 30, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3191
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit tester produces an output TEST signal following a pulse of a reference CLOCK signal with a delay that is a sum of an inherent drive delay and an adjustable drive delay. The tester also samples an input RESPONSE signal following a pulse of the reference CLOCK signal with a delay that is a sum of an inherent compare delay and an adjustable compare delay. The inherent drive and compare signal path delays within an integrated circuit tester are measured by first connecting a salphasic plane to transmission lines that normally convey signals between the tester and terminals of an integrated circuit device under test. A standing wave signal appearing on that salphasic plane is phase locked to the CLOCK signal so that a zero crossing of the standing wave occurs at a fixed interval after each pulse of the CLOCK signal. Each transmission line concurrently conveys the standing wave to the tester to provide timing references for measuring the inherent drive and compare signal path delays within the tester. Transmission line signal paths are also measured. Delays are added to the drive and compare signal paths to compensate for the measured inherent drive, compare and tra…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.