Wafer stack and method of producing sensors
US6106735A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 1998 |
| Grant date | Aug 22, 2000 |
| Priority date | — |
| Expiry date | Jan 12, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16235
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A wafer stack with sensor elements hermetically sealed in caverns and a method of fabricating the sensors permitting a reduction in the size of the sensors formed after cutting the wafer stack and also yielding considerable savings in chip area in the manufacture of the wafer stack. The wafer stack includes bonding strips arranged between the individual sensor elements. The wafer stack is diced to form individual sensors by sawing in the middle through the bonding strips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.