Method of manufacturing a DRAM capacitor
US6107132A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 1998 |
| Grant date | Aug 22, 2000 |
| Priority date | — |
| Expiry date | Dec 9, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
Abstract
A method of manufacturing a DRAM capacitor comprises the steps of providing a substrate having a word line, a source/drain region, a bit line and a first insulator layer. A hard mask layer and a second insulator layer are formed on the first insulator layer in sequence. Next, an opening is formed to expose a portion of the first insulator layer by patterning the second insulator layer and the hard mask layer. Thereafter, a spacer is formed on the side wall of the opening and a node contact hole is formed to expose a portion of the source/drain region in the first insulator layer. The second insulator layer is stripped to expose the hard mask layer and a conductive layer is formed over the hard mask layer and fills the node contact hole. A bottom electrode is formed by patterning the conductive layer and a dielectric layer and another conductive layer are formed over the bottom electrode in sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.