CMOS semiconductor device comprising graded junctions with reduced junction capacitance
US6107149A · kind A · utility
31Cited by
2References
13Claims
0Family size
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Key dates
| Filing date | Jun 4, 1999 |
| Grant date | Aug 22, 2000 |
| Priority date | — |
| Expiry date | Jun 4, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/917
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A CMOS semiconductor device is formed having an N-channel transistor comprising a graded junction with reduced junction capacitance. The graded junction is achieved by forming a second sidewall spacer on the gate electrode, after source/drain implantations, and ion-implanting an N-type impurity with high diffusivity, e.g., P into an A.sub.5 implant, followed by activation annealing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.