Thin film transistor with reduced parasitic capacitance and reduced feed-through voltage
US6107641A · kind A · utility
21Cited by
7References
19Claims
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Key dates
| Filing date | Sep 10, 1997 |
| Grant date | Aug 22, 2000 |
| Priority date | — |
| Expiry date | Sep 10, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/94
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved thin film transistor structure is provided having no source/gate or drain/gate overlap. A laser doping technique is applied to fabricate such transistors. Eliminating source/gate and drain/gate overlap significantly reduces or eliminates parasitic capacitance and feed-through voltage between source and gate. Short-channel a-Si:H thin film transistors may be obtained having high field effect mobilities. Improved pixel performance and pixel-to-pixel uniformity is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.