Sequentially built integrated circuit package
US6107683A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 1998 |
| Grant date | Aug 22, 2000 |
| Priority date | — |
| Expiry date | May 8, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An enhanced ball grid array substrate package and method for manufacturing the same, where the substrate package includes a metal core having a first surface and a second surface opposite the first surface. The metal core further includes at least one cavity in which at least one integrated circuit is positioned. A dielectric layer is secured to the first surface of the metal core and includes at least one die cavity formed therein. Thereafter, a conductive seed layer is chemically deposited to exposed portions of the dielectric layer and the first surface of the metal core. Adjacent to the conductive seed layer, a circuit is electrolytically and selectively formed within a first circuit pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.