Abram Castro
38Patents
10h-index
18Co-inventors
72Inventor score
Filing activity: Feb 6, 1995 → Nov 8, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7898083B2 | Method for low stress flip-chip assembly of fine-pitch semiconductor devices | Electricity | 91 | Active |
| US5650593A | Thermally enhanced chip carrier package | Electricity | 82 | Expired |
| US6107683A | Sequentially built integrated circuit package | Electricity | 64 | Expired |
| US7390700B2 | Packaged system of semiconductor chips having a semiconductor interposer | Electricity | 55 | Active |
| US6300165A | Ball grid substrate for lead-on-chip semiconductor package | Electricity | 44 | Expired |
| US6534861B1 | Ball grid substrate for lead-on-chip semiconductor package | Electricity | 28 | Expired |
| US8133761B2 | Packaged system of semiconductor chips having a semiconductor interposer | Electricity | 17 | Active |
| US7569918B2 | Semiconductor package-on-package system including integrated passive components | Electricity | 10 | Active |
| US7573139B2 | Packed system of semiconductor chips having a semiconductor interposer | Electricity | 10 | Active |
| US6801438B1 | Electrical circuit and method of formation | Electricity | 10 | Expired |
| US6248612A | Method for making a substrate for an integrated circuit package | Electricity | 9 | Expired |
| US6501168B1 | Substrate for an integrated circuit package | Electricity | 8 | Expired |
| US9305869B1 | Packaged semiconductor device having leadframe features as pressure valves against delamination | Electricity | 6 | Active |
| US9214440B1 | Method for preventing die pad delamination | Electricity | 3 | Active |
| US9780017B2 | Packaged device with additive substrate surface modification | Electricity | 2 | Active |
| US9524926B2 | Packaged device with additive substrate surface modification | Electricity | 2 | Active |
| US9129955B2 | Semiconductor flip-chip system having oblong connectors and reduced trace pitches | Electricity | 2 | Active |
| US9875930B2 | Method of packaging a circuit | Electricity | 1 | Active |
| US11495524B2 | QFN device having a mechanism that enables an inspectable solder joint when attached to a PWB and method of making same | Electricity | 1 | Active |
| US8530360B2 | Method for low stress flip-chip assembly of fine-pitch semiconductor devices | Electricity | 1 | Active |
| US9601414B2 | Method for preventing die pad delamination | Electricity | 0 | Active |
| US9142472B2 | Integrated circuit and method of making | Electricity | 0 | Active |
| US11854947B2 | Integrated circuit chip with a vertical connector | Electricity | 0 | Active |
| US10199348B2 | Plastic-packaged semiconductor device having wires with polymerized insulating layer | Electricity | 0 | Active |
| US11177195B2 | Multi-lead adapter | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.