Redundancy circuitry for programmable logic devices with interleaved input circuits
US6107820A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 1998 |
| Grant date | Aug 22, 2000 |
| Priority date | — |
| Expiry date | May 20, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1778
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Redundant circuitry is provided for a programmable logic device that uses an interleaved input multiplexer circuit arrangement. The programmable logic device has at least one row of logic regions and has multiple columns, each of which contains one of the interleaved input multiplexers and one of the logic regions. A set of conductors associated with the row of logic regions is used to convey signals between the logic regions. Each interleaved logic region distributes logic signals from the conductors in the row to two adjacent logic regions. Bypass circuitry is provided in each column for bypassing the interleaved input multiplexer and logic region in that column. If a defect is detected in a column during testing of the device, the manufacturer can repair the device using the bypass circuitry to bypass that column. Spare logic is provided to replace the circuitry lost when a defective column is bypassed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.