Model for taking into account gate resistance induced propagation delay
US6110219A · kind A · utility
7Cited by
5References
40Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 24, 1997 |
| Grant date | Aug 29, 2000 |
| Priority date | — |
| Expiry date | Jul 24, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
When simulating a circuit's behavior, a transistor can be modeled to account for gate resistance induced propagation delay. In one embodiment, the model includes a transistor with a resistor connected to the gate of the transistor. The resistor has a resistance equal to one third of the gate resistance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.