Method for fabricating a MOS device

US6110787A · kind A · utility

Assignee

• Chartered Semiconductor Manufacturing LTD · SG

Inventors

• Lap Chan · San Francisco, US
• Ting Cheong Ang · Shanghai, CN
• Shyue Pong Quek · Petaling Jaya, MY
• Sang Yee Loong · Singapore, SG

Key dates

• Filing date: Sep 7, 1999
• Grant date: Aug 29, 2000
• Expiry date: Sep 7, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/259
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of fabricating a MOS device having raised source/drain, raised isolation regions having isolation spacers, and a gate conductor having gate spacers is achieved. A layer of gate silicon oxide is grown over the surface of a semiconductor structure. A polysilicon layer is deposited overlying the gate silicon oxide layer. The polysilicon layer, gate silicon oxide layer and semiconductor structure are patterned and etched to form trenches. The trenches are filled with an isolation material to at least a level even with a top surface of the polysilicon layer to form raised isolation regions. The remaining polysilicon layer is patterned to remove polysilicon adjacent the raised isolation regions forming a gate conductor between the raised isolation regions. The gate conductor and the raised isolation regions having exposed sidewalls. The gate oxide layer between the gate conductor and raised isolation regions is removed. Isolation spacers are formed on the exposed sidewalls of the raised isolation regions and gate spacers are formed on the exposed sidewalls of the gate conductor. A layer of silicon is deposited and patterned to form raised source and drain adjacent the gate space…