Method and apparatus for adjusting control signal timing in a memory device
US6111812A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 1999 |
| Grant date | Aug 29, 2000 |
| Priority date | — |
| Expiry date | Jul 23, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus is described for selectively adjusting control signal timing in a memory device as a function of the externally applied system clock speed. The memory device includes clock sensing circuitry that receives the system clock signal and responsively produces a speed signal having a value corresponding to the frequency of the system clock signal. The clock sensing circuitry includes a plurality of series-connected time-delay circuits through which a signal derived from the system clock signal propagates. The clock sensing circuitry also includes a plurality of latch circuits, each coupled with a respective one of the time delay circuits and latching the value of the signal reaching the respective time delay circuit. The speed signal is then derived from these latched signal values, indicating through how many of the time-delay circuits the signal has propagated. The memory device also includes a control signal delay circuit that receives an internal memory control signal and the speed signal, and responsively produces a delayed control signal having a time delay corresponding to the speed signal value. The control signal delay circuit includes a plurality of serie…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.