Computer aided design system and method using hierarchical and flat netlist circuit representations
US6113647A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 1996 |
| Grant date | Sep 5, 2000 |
| Priority date | — |
| Expiry date | Nov 6, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A set of flat net descriptors are added to a hierarchical representation of a specified circuit design so as to provide a hierarchical view and a flat net view of the circuit design. The hierarchical representation includes a set of cell descriptors representing hierarchical cells in the specified circuit design, and a set of net descriptors representing portions of interconnections located within each hierarchical cell. Each net descriptor has associated therewith a list of endpoint descriptors representing endpoints of a corresponding one of the interconnections located within a respective hierarchical cell. The procedure for generating flat nets generates a flat net descriptor for each interconnection in the specified circuit. Each flat net descriptor has associated therewith a list of endpoint descriptors representing all endpoints of the interconnection. Each of the endpoint descriptor associated with a flat net descriptor represents an interconnection endpoint in a flat, top level circuit representation of the specified circuit design. A flat net pointer is added to each net descriptor in the hierarchical representation of the specified circuit design. The flat net pointer po…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.