Nitrogen ion implanted amorphous silicon to produce oxidation resistant and finer grain polysilicon based floating gates

US6114230A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Kent Kuohua Chang · Cupertino, US
• Yuesong He · San Jose, US
• David Chi · Sunnyvale, US

Key dates

• Filing date: Dec 18, 1997
• Grant date: Sep 5, 2000
• Expiry date: Dec 18, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

A polysilicon-based floating gate is formed so as to be resistant to oxidation that occurs during multiple thermo-cycles in fabrication. Accordingly, edge erase times in NOR-type memory devices may be minimized. Additionally, manufacture of oxidation resistant floating gates reduces variations in edge erase times among multiple NOR-type memory devices. A layer of amorphous silicon is deposited over a silicon substrate by directing a mixture of silane and a phosphene-helium gas mixture at the surface of the silicon substrate. Later, N+ ions are implanted into the amorphous silicon. The amorphous silicon layer is then etched so as to overlap slightly with regions that will later correspond to the source and drain regions. Next, a lower oxide layer of an ONO dielectric is deposited and the device is heated. A thermo-cycle is eliminated by heating the amorphous silicon during formation of the oxide layer rather than immediately following its deposition. Later, the nitride and oxide layers of the ONO dielectric, a second polysilicon layer, a tungsten silicide layer, and SiON layers are successively formed.