Techniques for etching a low capacitance dielectric layer on a substrate
US6114250A · kind A · utility
33Cited by
12References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 17, 1998 |
| Grant date | Sep 5, 2000 |
| Priority date | — |
| Expiry date | Aug 17, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31138
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for etching through a low capacitance dielectric layer in a plasma processing chamber. The low capacitance dielectric layer is disposed below a hard mask layer on a substrate. The method includes flowing an etch chemistry that includes N.sub.2 and H.sub.2 into the plasma processing chamber. There is included creating a plasma out of the etch chemistry. The method also includes etching, using the plasma, through the low capacitance dielectric layer through openings in the hard mask layer in the plasma processing chamber.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.