Integrated circuit with metal features presenting a larger landing area for vias
US6114766A · kind A · utility
21Cited by
3References
27Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 18, 1997 |
| Grant date | Sep 5, 2000 |
| Priority date | — |
| Expiry date | Dec 18, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A metal feature, defined by gaps in a patterned metal layer, is formed with an inwardly tapering profile so that it is wider at the top than at the bottom. The metal feature advantageously presents a larger landing area for vias while maintaining the dimensions and intraline coupling capacitance requited by design. The gaps in the patterned metal layer can be filled with a spin-on dielectric material such as spin-on glass (SOG) or hydrogen silsesquioxane (HSQ).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.