Method and apparatus for testing memory devices
US6115303A · kind A · utility
4Cited by
16References
36Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 9, 1998 |
| Grant date | Sep 5, 2000 |
| Priority date | — |
| Expiry date | Oct 9, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A test circuit for functionally testing memory devices. The test circuit loads a plurality of data bits into the memory device under test. The test circuit subsequently reads the data bits stored in the memory cells, and detects if the logic level of the data bits read is the complement of the logic level written: The logic level is detected over a duration during which at least two data bits are read.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.