Clock vernier adjustment
US6115318A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 3, 1996 |
| Grant date | Sep 5, 2000 |
| Priority date | — |
| Expiry date | Dec 3, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A integrated circuit, such as a memory integrated circuit, includes a vernier clock adjustment circuit receiving an input clock signal and providing a rising-edge clock signal representing the input clock signal delayed by a rising-edge delay and providing a falling-edge clock signal representing the input clock signal delayed by a falling-edge delay. An edge triggered circuit receives data and the rising-edge and falling-edge clock signals, and stores data at the rising-edge of the rising-edge clock signal and at the falling-edge of the falling-edge clock signal. One form of the invention is a memory system having a memory controller coupled to memory modules through data and command busses. Each memory module includes the vernier clock adjustment circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.