Methods of electroplating solder bumps of uniform height on integrated circuit substrates
US6117299A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 1997 |
| Grant date | Sep 12, 2000 |
| Priority date | — |
| Expiry date | May 9, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of electroplating solder bumps of uniform height on integrated circuit substrates include the steps of drawing plating current through an integrated circuit wafer by electrically shorting an integrated circuit's ground, power and signal pads together using an ultra-thin plating base layer (e.g., <0.075 .mu.m thick) and then using a backside wafer contact to draw electroplating current along parallel paths which extend through the ground and signal pads and into the substrate. The ground pads are preferably electrically coupled to the substrate at substrate contact regions (e.g., N + or P + diffusion regions) and the signal pads are preferably electrically coupled to the substrate through active semiconductor devices (e.g., FETs, BJTs, . . . ) to which the signal pads are attached. Plating current is preferably drawn in parallel through an integrated circuit's active semiconductor devices and substrate contact regions. The combined contributions of the plating currents drawn through the substrate contact regions and the active semiconductor devices is sufficient to maintain the plating base layer and underlying pads at uniform potentials even though the plating base layer ha…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.