Integration of MOM capacitor into dual damascene process
US6117747A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 1999 |
| Grant date | Sep 12, 2000 |
| Priority date | — |
| Expiry date | Nov 22, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/692
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a metal-oxide-metal capacitor using a dual damascene process is described. A dielectric layer is provided overlying a semiconductor substrate. A dual damascene opening in the dielectric layer is filled with copper to form a copper via underlying a copper line. A first metal layer is deposited overlying the copper line and patterned to form a bottom capacitor plate contacting the copper line. A capacitor dielectric layer is deposited overlying the bottom capacitor plate. A second metal layer is deposited overlying the capacitor dielectric layer and patterned to form a top capacitor plate to complete fabrication of a metal-oxide-metal capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.